The invention relates to delay locked loop-based circuits, and in particular to delay locked loop-based circuits in data communication.
Circuits using phase locked loop (PLL) are widely used in data communications. An example of such a circuit may be a data recovery circuit. A PLL based circuit may be generally sufficient where power dissipation is not an issue even though communication speeds are high. In certain circuits, the communication speeds may range from 1 MHz to 100 GHz. In general, however, circuits operating at high speeds are sensitive to power dissipation that results in the overheating of the circuits. In circuits where power conservation is an issue, power dissipation is also problematic.
One commonly used method of reducing power dissipation is to place the circuit in xe2x80x9csleep modexe2x80x9d when not in use. In the sleep mode, the circuit is temporarily shut down until reactivated which is generally referred to as xe2x80x9cwake upxe2x80x9d. For example, when no transmission is being received, the data recovery circuit places itself in a sleep mode. When a transmission is detected, the data recovery circuit wakes up to process the transmission. However, the PLL in the data recovery circuit generally requires a substantial acquisition time, perhaps in the order of 94 to 2000 cycles before the PLL can lock onto the incoming transmission. Therefore, to allow for the PLL lock, synchronizing signals of sufficient duration are transmitted before the actual transmission is transmitted. However, such synchronizing signals introduce latency to the overall data transfer speed, which is problematic in high-speed data communication. In one method, latency due to PLL acquisition time is minimized by transmitting synchronizing signals at predetermined intervals to the data recovery circuit during sleep mode thereby allowing the PLL to maintain lock. However, the transmitter circuit and the data recovery circuit are not fully in the sleep mode resulting in a constant power dissipation.
The PLL also has poor jitter tolerance in that being an analog device, which uses a voltage-controlled oscillator, the PLL inherently generates noise. Furthermore, the PLL of the data recovery circuit syncs with the transmitting clock to recover data. However, because the recovered data is not in sync with the recovery circuit clock, the data needs to be resynced using an additional re-timing circuit. As an additional problem, being an analog circuit, the PLL -based data recovery circuit is rather complicated and cannot be easily implemented in a CMOS fabrication process. Therefore, generally, two fabrication processes are performed. First, a CMOS fabrication process is performed to implement the digital circuits in the substrate. This is followed by a bipolar fabrication process to implement the analog circuits in the substrate. However, using two processes complicates the manufacturing process and is generally not cost efficient. In addition, PLL-based circuits are highly susceptible to the stray resistance and capacitance of the substrate. In many instances, the effects of the stray resistance and capacitance of the substrate are so severe that the characteristics of the original PLL design are altered. Thus, the PLL does not perform according to its specification. Due to this problem, the PLL design may not be readily scalable and may depend on the characteristics of the particular substrate in which the PLL is to be implemented.
Being an analog device and having additional circuitry such as a re-timing circuit, data recovery circuits based on PLL are generally large using large areas of the silicon substrate. Accordingly, it is desired to design a data communication circuit that does not require an analog circuitry like the PLL and overcomes the shortcomings described above.
In accordance with the invention, there is disclosed an apparatus including a sampling circuit to generate sampling clocks from a local clock and the sampling clocks to sample incoming data and a quarter clock, a phase detector to detect a phase difference between a data transition in sampled data and the local clock, and a delay line adapted to delay the sampled data by the detected phase difference.